The present invention relates to an etching mask, a process for forming contact holes using the same etching mask, and a semiconductor device which is manufactured by the same process.
With an recent advance in high integration density and smaller size of semiconductor devices, the area of each element has been remarkably reduced. However, the thickness of the films therefor should be increased if the same materials are used since it is necessary to provide an electric resistance which is equal to or less than that of the conventional semiconductor devices. Thus, the thickness of the interlayer films will increase, so that a case where contact holes in the second and subsequent films require a depth which is 3 xcexcm or more is not rare. Since the diameter of the contact holes has become smaller and smaller, the technique to fabricate contact holes having a higher aspect ratio at a high precision has been demanded.
A process for forming contact holes in the course of manufacturing conventional general DRAM (Dynamic Random Access Memory) process will now be described with reference to the drawings. FIGS. 10 through 12 are sectional views schematically showing a conventional process for manufacturing a DRAM. For convenience of drawing, these drawings are separated with an alphabetical sequence.
After an element isolation oxide film 2 is formed in a given region of a silicon substrate 1 by a trench isolation method as shown in FIG. 10(a), memory regions and peripheral circuit regions are formed. Well-regions 8 are formed by implanting ions of phosphorous, boron, etc. into respective regions. A gate oxide film 3, gate electrode film 4 and silicon nitride film 5 are successively deposited on the silicon substrate 1, and gate electrodes are formed by etching process, source/drain regions 7 are formed by the implantation of ions of phosphorus and the like.
Subsequently, after a silicon oxide film is deposited to cover the gate electrodes as shown in FIG. 10(b), side walls 6 are formed by applying an anisotropic etching and n+/p+ layers are formed by protecting given regions with a resist and implanting ions of phosphorus and boron, etc.
Then, a first interlayer film 9 is deposited over an entire surface of the silicon substrate 1 as shown in FIG. 10(c) and a resist pattern 22 is formed in such a manner that regions to be connected to bit lines are exposed. Contact holes are formed in the first interlayer film 9 by plasma etching using the resist pattern 22 as an etching mask and using a carbon fluoride (CF system) gas.
In order to enhance the precision of the size of openings of the resist pattern 22 by eliminating the influence of the reactivity with the underlying layer (or substrate) and the reflected light from the underlying layer (or substrate) on formation of the resist pattern 22, an antireflection coating (hereinafter referred to as ARC) 28 may be formed between the first interlayer film 9 and the resist 22. In this case, hole is first formed in the ARC using oxygen gas by plasma etching with the aid of the resist pattern 22 as a mask. Thereafter, the first interlayer film 9 is formed leaving a contact hole 10 by the plasma etching using CF gas. The ARC 28 will be removed together with the resist pattern 22 after formation of the first contact hole 10.
Then, a bit line (first film wiring 11) which is to be connected to polysilicon is formed after polysilicon (and the like) is buried in the first contact hole 10 as shown in FIG. 10(d).
Subsequently, after a silicon oxide film 12 is deposited over an entire surface of the silicon substrate 1 and the resist pattern 22 is formed so that a region which is to be connected to storage nodes will be exposed as shown in FIG. 11(e), (second) contact holes which extends through the silicon oxide film 9 are formed by a plasma etching using the resist pattern 22 as an etching mask and using an CF gas. An ARC 28 may also be formed on the silicon oxide film 12 in order to prevent the influence of underlying substrate in the course of the resist pattern forming process. In this case, the ARC is firstly subjected to boring (hole-opening) by the plasma etching with oxygen gas. Thereafter, the (second) contact holes are formed in the silicon oxide film 12 and the first interlayer film 9 by using CF gas.
After polysilicon, etc is buried in second contact holes 13 as shown in FIG. 11(f), a metal film (second layer wiring 14) which will be connected to polysilicon is formed, and a high dielectric thin film and a metal film are subsequently formed thereon, so that a capacitor 15 comprising a dielectric thin film which is sandwiched between the metal films is formed.
Subsequently, a second interlayer film 16 is deposited over the entire surface of the silicon substrate 11 and a resist pattern 22 is formed in such a manner that regions which are connected to the source/drain regions 7 and the capacitor 15 are exposed as shown in FIG. 11(g). Third contact holes extending through the second interlayer film 16, silicon oxide film 12 and first interlayer film 9 and a fourth contact hole extending through the second interlayer film 16 are formed by the plasma etching using the resist pattern 22 as an etching mask and using CF gas. In this process, the ARC may also be similarly formed for canceling the influence of an underlying layer (or layers).
Then, after titanium and titanium nitride is buried in a fourth contact hole 18 which is connected with the capacitor 18 and titanium nitride is buried in the third contact holes 17 which are connected to the source/drain regions 7 as shown in FIG. 12(h), titanium silicide is formed in the source/drain regions 7 by conducting heat treatment.
After a third layer wiring 19 is formed by depositing a film of a metal such as Al as shown in FIG. 12(i), a DRAM is formed by depositing an interlayer insulating film and a passivation film (not shown) thereon.
In the above-mentioned process for manufacturing DRAM, there is a tendency that the contact holes shown in FIGS. 11(e) and 11(g) will have an increased aspect ratio in association with the reduction in the size of the device and the enhanced performance thereof. It is of great importance in the manufacturing of DRAM how the contact holes can be opened at high precision.
The resist patterns have heretofore been used as an etching mask when such contact holes are opened. However, there are problems in that the openings (i.e., hole edges) of the resist will gradually increase, so that the opening diameter of the contact holes will also increase since the resist per se is also etched on dry etching for forming the contact holes and in that the thickness of the resist may be reduced. On the other hand, the thickness of the resist tends to decrease in association with the reduction in the size of the devices. The resist is not endurable against the dry etching for an extended period of time.
The last problem will be explained with reference to FIGS. 13 and 14 in more detail. FIGS. 13 and 14 are sectional views schematically showing a process for forming contact holes by using a conventional resist pattern as an etching mask. In FIG. 14, an antireflection film 28 of an organic material is formed on a silicon oxide film 20 for canceling the activity with the underlying layer(s) and the influence of the underlying layer(s).
In the conventional process for forming contact holes, the resist pattern having a film thickness of about 700 nm has been formed on an inorganic interlayer film 20 such as silicon oxide film having a thickness of 3 xcexcm as shown in FIG. 13 and the contact holes have been formed by the plasma etching using a fluorocarbon mixture gas (termed herein xe2x80x9cCF gasxe2x80x9d)). Since the film thickness of the resist is gradually reduced and the diameter of the opening becomes gradually larger, the opening diameter of the contact holes (edges) becomes larger than that in the initial resist pattern.
In particular, in a case where the inorganic ARC 28 is formed on the silicon oxide film 20 as shown in FIG. 14, oxygen should be mixed with the etching gas for dry etching for opening holes in the ARC 28. Mixing of oxygen promotes the etching of the resist, so that the diameter of the opening of the contact holes will further increase.
In order to overcome the above mentioned problem, an approach to use polysilicon and the like as an etching mask in lieu of the resist has been considered. If polysilicon is used as a mask, it is possible to provide a higher etching selectivity of the polysilicon than that of the resist for the CF gas. The Si may react with CF gas is high and the vapor pressure of the product of the reaction may become high. Accordingly, polysilicon is not suitable for the material of the etching mask. Since polysilicon is not dielectric, it should be removed after formation of the contact holes. However, it is hard to selectively remove only polysilicon after opening of the contact holes.
A method to use Si3N4 as an etching mask has also been proposed. This method can be used in a case where the contact holes are formed to extend through a silicon oxide film. However, it is not possible to provide an etching selectivity if the contact holes should be also formed to extend through the silicon nitride film, for example, the silicon nitride film of the gate electrode.
Generally, the present invention has been achieved encountering the above-mentioned problems.
It is an object according to an aspect of the present invention to provide a novel etching mask which is capable of forming contact holes having a high aspect ratio and assures a high etching selectivity for SiO2 and Si3N4 as well as organic ARC, interlayer film and electrically conductive film.
It is another object according to another aspect of the present invention to provide a novel process for forming contact holes using the same mask.
It is a further object according to a further aspect of the present invention to provide a novel semiconductor device which is formed by the process.
Other objects and aspects of the present invention will become apparent in the entire disclosure.
In a first aspect of the present invention, there is provided an etching mask used for forming contact holes to connect wiring layers which sandwich an interlayer film therebetween, wherein the etching mask comprises or is formed of silicon carbide.
In a second aspect of the present invention, there is provided a process for forming contact holes to connect wiring layers which sandwich an interlayer film therebetween comprising the steps of: forming a thin film of silicon carbide on an interlayer film through which said contact holes will be formed; forming a resist pattern on said silicon carbide film; dry-etching said exposed portions of said silicon carbide film using said resist pattern as a mask; removing said resist pattern by dry or wet-etching; and forming contact holes through said interlayer film using said silicon carbide film as a mask.
In a third aspect of the present invention, there is provided a semiconductor device in which wiring layers on and under an interlayer film are connected to one another through contact holes which are formed to extend through the interlayer film, wherein an insulating film made of silicon carbide is disposed between the interlayer film and the wiring layer disposed thereon.
In a fourth aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; at least one gate electrode and source/drain regions thereon; and a plurality of interlayer films and a plurality of wiring layers which are stacked on the gate electrode. The gate electrode(s) and said wiring layers being connected to one another through contact holes formed to extend through the interlayer films. The device is characterized in at least one of the contact holes is formed so as to extend through a silicon nitride film which is disposed to cover the gate electrode(s) and one of the interlayer films which is deposited on the gate electrode.
Particularly, the contact holes are formed using a silicon carbide film as an etching mask, resulting in a sharp opening edge of the contact holes to provide a high aspect ratio of the contact holes as well as selective etching capability.